JEDEC JESD217
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES
standard by JEDEC Solid State Technology Association, 09/01/2010
JEDEC JEP132 (R2007)
PROCESS CHARACTERIZATION GUIDELINE
standard by JEDEC Solid State Technology Association, 07/01/1998
JEDEC JESD82-19A
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
JEDEC JESD84-B451
Embedded Multi-media card (e*MMC), Electrical Standard 4.51
standard by JEDEC Solid State Technology Association, 06/01/2012
JEDEC JESD79-3-3
Addendum No. 1 to 3D Stacked SDRAM
Amendment by JEDEC Solid State Technology Association, 12/01/2013
JEDEC JESD47I
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2011
JEDEC JESD47H
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 02/01/2011
JEDEC JS-001-2017
ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level
standard by JEDEC Solid State Technology Association, 05/12/2017
JEDEC JESD82-31
DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)
standard by JEDEC Solid State Technology Association, 08/01/2016
JEDEC JEP158
3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
standard by JEDEC Solid State Technology Association, 11/01/2009